Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making

ABSTRACT

A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

RELATED APPLICATIONS

This application is a divisional of Herner, U.S. patent application Ser.No. 10/611,245, “Low-Density, High-Resistivity Titanium Nitride Layerfor Use as a Contact for Low-Leakage Dielectric Layers,” filed Jun. 30,2003, assigned to the assignee of the present invention and herebyincorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

Many semiconductor devices include a dielectric layer between twoconductors. If this dielectric is imperfect, leakage current across thedielectric may adversely affect device performance.

The invention relates to the use in semiconductor devices of alow-density, high-resistivity metal layer, preferably titanium nitride.Paired with a dielectric, the layer reduces leakage current across thedielectric.

It is known in the art that ionized metal plasma deposition of titaniumnitride with no applied self-bias creates a low-density,high-resistivity titanium nitride (see Tanaka et al., “Properties oftitanium nitride film deposited by ionized metal plasma source,” Journalof Vacuum Science Technology, March/April 1999), but the usefulness ofthis material in semiconductor devices according to the presentinvention has not been previously recognized.

SUMMARY OF THE INVENTION

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. Ingeneral, the invention is directed to a low-density, high-resistivitymaterial which can be paired with a dielectric to form a low-leakagecontact, and its use in semiconductor devices.

A first aspect of the invention provides for a method for formingtitanium nitride in a semiconductor device comprising providing asurface for a semiconductor device; and depositing a film of titaniumnitride on the surface by physical vapor deposition wherein, for anyportion of the film more than about 20 angstroms thick, the density ofthe titanium nitride is less than about 4.0 grams per cubic cm.

Another aspect of the invention provides for a semiconductor devicecomprising a first conductive or semiconductive material; a layer oftitanium nitride, wherein, for any portion of the titanium nitride layermore than about 20 angstroms thick, the resistivity of the titaniumnitride is greater than about 300 microOhm-cms and the density is lessthan about 4.25 grams per cubic cm; and a dielectric layer interposedbetween the first conductive or semiconductive material and the titaniumnitride layer.

Yet another aspect of the invention calls for a semiconductor devicecomprising silicon; in contact with the silicon, a layer of silicondioxide or silicon nitride; and in contact with the silicon dioxide orsilicon nitride layer, a layer of nitrogen-rich titanium nitride,wherein, for any portion of the titanium nitride layer more than about20 angstroms thick, the ratio of titanium to nitrogen is greater thanabout 1.2:1 and the density is less than about 4.0 grams per cubic cm.

A preferred embodiment provides for a method for making a thin filmtransistor comprising forming a polysilicon layer; forming a silicondioxide layer in contact with the polysilicon layer; forming a titaniumnitride layer in contact with the silicon dioxide layer wherein, for anyportion of the titanium nitride layer more than about 20 angstromsthick, the resistivity of the titanium nitride is greater than about 300microOhm-cms and the density of the titanium nitride is less than about4.25 grams per cubic cm; and patterning and etching the titaniumnitride.

Another embodiment provides for a monolithic three dimensional memoryarray comprising polysilicon; in contact with the polysilicon, a layerof silicon dioxide or silicon nitride; and in contact with the silicondioxide or silicon nitride layer, a layer of titanium nitride, wherein,for any portion of the titanium nitride layer more than about 20angstroms thick, the resistivity of the titanium nitride is greater thanabout 300 microOhm-cms and the density of the titanium nitride is lessthan about 4.25 grams per cubic cm.

An aspect of the invention provides for a method for forming titaniumnitride in a semiconductor device comprising providing a surface for asemiconductor device; and depositing on the surface a film of titaniumnitride by physical vapor deposition wherein, for any portion of thefilm more than about 20 angstroms thick, the deposition is performedwith substantially no self-bias and with pressure greater than about 15mTorr.

Another aspect of the invention provides for a method for formingtitanium nitride for use in a semiconductor device comprising providinga surface for a semiconductor device; on the surface, depositingtitanium nitride wherein, for any portion of the titanium nitride layermore than about 20 angstroms thick, the resistivity of the titaniumnitride is greater than about 300 microOhm-cms and the ratio of nitrogento titanium is greater than about 1.2:1.

A preferred embodiment provides for a semiconductor device comprising adielectric-rupture antifuse; and a layer of low-density,high-resistivity material in contact with the antifuse wherein thelow-density, high-resistivity material is titanium nitride, tungstennitride, tantalum nitride, titanium tungsten, tungsten, or aluminum, andwherein a portion of the low-density, high-resistivity material having athickness greater than about 20 angstroms was deposited by physicalvapor deposition in a chamber with substantially no self-bias.

Another aspect of the invention provides for a semiconductor devicecomprising a dielectric layer; a titanium nitride layer in contact withthe dielectric layer wherein, for any portion of the titanium nitridelayer thicker than about 20 angstroms, the ratio of nitrogen to titaniumis greater than about 1.2:1, and wherein, for any portion of thetitanium nitride layer thicker than about 20 angstroms, the resistivityof the titanium nitride layer is greater than about 300 microOhm-cms.

A preferred embodiment provides for a method for forming titaniumnitride in a semiconductor device comprising providing a surface for asemiconductor device; and depositing a film of titanium nitride on thesurface by physical vapor deposition wherein the density of the titaniumnitride is less than about 4.0 grams per cubic cm.

Another preferred embodiment provides for a semiconductor devicecomprising a first conductive or semiconductive material; a layer oftitanium nitride the resistivity of the titanium nitride is greater thanabout 300 microOhm-cms and the density is less than about 4.25 grams percubic cm; and a dielectric layer interposed between the first conductiveor semiconductive material and the titanium nitride layer.

Yet another preferred embodiment provides for a semiconductor devicecomprising silicon; in contact with the silicon, a layer of silicondioxide or silicon nitride; and in contact with the silicon dioxide orsilicon nitride layer, a layer of nitrogen-rich titanium nitride,wherein the ratio of titanium to nitrogen is greater than about 1.2:1and the density is less than about 4.0 grams per cubic cm.

Another preferred embodiment provides for a method for making a thinfilm transistor comprising forming a polysilicon layer; forming asilicon dioxide layer in contact with the polysilicon layer; forming atitanium nitride layer in contact with the silicon dioxide layer whereinthe resistivity of the titanium nitride is greater than about 300microOhm-cms and the density of the titanium nitride is less than about4.25 grams per cubic cm; and patterning and etching the titaniumnitride.

Still another preferred embodiment provides for a monolithic threedimensional memory array comprising polysilicon; in contact with thepolysilicon, a layer of silicon dioxide or silicon nitride; and incontact with the silicon dioxide or silicon nitride layer, a layer oftitanium nitride, wherein the resistivity of the titanium nitride isgreater than about 300 microOhm-cms and the density of the titaniumnitride is less than about 4.25 grams per cubic cm.

An aspect of the invention provides for a memory array comprising memorycells on a die, wherein the memory cells comprise diode portions and anantifuse, wherein the diode portions comprise doped polysilicon, andwherein median leakage current across the antifuse for the memory cellson the die is less than about 1.77×10⁻¹³ amps/μm².

Another aspect of the invention provides for a semiconductor devicecomprising an antifuse; and a layer of low-density, high-resistivitymaterial in contact with the antifuse, such that the leakage currentacross the antifuse in contact with the low-density, high-resistivitymaterial is less than one-tenth the leakage current across an identicalantifuse in contact with an analogous material when the analogousmaterial is formed in the presence of self-bias or decreased pressure.

Still another aspect of the invention provides for a semiconductordevice comprising an antifuse; and a layer of low-density,high-resistivity material in contact with the antifuse, wherein thedensity of the low-density, high-resistivity material is less than about75 percent of the material's theoretical density, such that the leakagecurrent across the antifuse in contact with the low-density,high-resistivity material is less than one-tenth the leakage currentacross an identical antifuse in contact with an analogous material whenthe density of the analogous material is substantially equivalent to itstheoretical density.

Each of the aspects of the invention and embodiments can be used aloneor in combination with one another.

The preferred embodiments will now be described with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a memory cell according to thepresent invention.

FIGS. 2 a and 2 b are cross-sectional views showing physical vapordeposition with and without self-bias.

FIG. 3 is a TEM image showing both low-density and higher-densitytitanium nitride.

FIG. 4 is a chart comparing leakage current across antifuses of devicesformed with and without the low-density, high-resistivity titaniumnitride used in the present invention.

FIG. 5 is a chart comparing current after rupture of the antifuse indevices formed with and without the low-density, high-resistivitytitanium nitride used in the present invention.

FIG. 6 is a cross-sectional view of a Schottky diode according to thepresent invention.

FIG. 7 is a cross-sectional view of a field effect transistor accordingto the present invention.

FIG. 8 is a cross-sectional view of a SONOS-type device according to thepresent invention.

FIG. 9 is a cross-sectional view of a floating gate memory cellaccording to the present invention.

FIG. 10 is a cross-sectional view of a capacitor according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

Many semiconductor devices require a conductor or semiconductor to beseparated from another conductor or semiconductor by a dielectric (anelectrical insulator.) All dielectrics will allow some current to flowunder an applied biasing voltage. This current is called leakagecurrent, and adversely affects device performance. Some such devicesinclude permanent dielectrics, as in capacitors and field effecttransistors. Others include dielectric rupture antifuses, which providean insulator until the antifuse is ruptured.

The present invention calls for use of a low-density high-resistivityconductor, preferably produced by sputtering. The conductor is titaniumnitride, tungsten nitride, tantalum nitride, titanium tungsten,tungsten, or aluminum, preferably titanium nitride. In some embodiments,the conductor is not stoichiometric (a compound is stoichiometric whenits ratio of cations to anions is exactly that specified by its chemicalformula.) The ratio of nitrogen to titanium, rather than 1:1, may bemore than about 1.2:1, preferably between about 1.3:1 and 1:4:1.

Herner et al., U.S. patent application Ser. No. 10/326470, “An ImprovedMethod for Making High Density Nonvolatile Memory,” filed Dec. 19, 2003and hereby incorporated by reference, (henceforth the '470 application)uses this low-density, high-resistivity titanium nitride in a monolithicthree dimensional memory array. In embodiments of this memory array, asshown in FIG. 1, each memory cell 100 comprises a vertically-orientedpost-shaped PN diode 102 with an antifuse 104 formed on top of thediode. The antifuse 104 separates and electrically isolates the diode102 from an overlying conductor 110. The bottom layer 106 of conductor110 is preferably low-density, high-resistivity titanium nitride asdescribed herein. Use of this low-density, high-resistivity titaniumnitride in the '470 application is the work of the present inventor.Layer 108 is a conductor, preferably tungsten. The memory cell 100 isprogrammed by applying a high voltage across antifuse 104. When such avoltage is applied, the antifuse is ruptured, and current can flowbetween diode 102 and conductor 110. Ideal device performance calls forminimal leakage current before antifuse rupture, and good contact after.

When made according to the instructions provided in the '470application, leakage current between diode 102 and the overlyingconductor 110 is unexpectedly low before the antifuse 104 is ruptured.The nature of the titanium nitride forming the bottom layer 106 of theconductor proves to be the reason for this low leakage. An analogouslow-leakage barrier could also be formed using tungsten nitride,tantalum nitride, titanium tungsten, tungsten, or aluminum. (If antifuse104 is silicon dioxide, however, tungsten and aluminum are lessadvantageous choices, as tungsten does not adhere well to silicondioxide and aluminum reduces silicon dioxide.)

This titanium nitride layer is deposited by sputtering or physical vapordeposition (PVD.) Sputtering or PVD is performed either with or withoutapplied self-bias voltage, which accelerates metal ions in the directionnormal to the substrate. Titanium nitride may be deposited by an ionizedmetal plasma (IMP) method, a PVD method normally applying self-bias.This acceleration toward the substrate, shown in FIG. 2 a, helps assuregood bottom coverage in trenches. In this method, a titanium target issputtered with a mixture of Ar and N₂ gas. A plasma is generated byapplying RF power to an inductive coil located inside the chamber.

Normally IMP PVD films are deposited at higher pressures (about 20mTorr) than PVD processes without self-bias (these are normallydeposited at about 0.5 to about 5 mTorr.) Both processes produce dense,low-resistivity films. However, when a film is sputtered at higherpressure without self-bias (as in FIG. 2 b), the film is low densitywith increased resistivity. The films can also have a higher ratio ofnitrogen to titanium than films deposited at lower pressure. Thislow-density, high-resistivity titanium nitride, when paired with adielectric, provides a very low-leakage barrier and can be usefullyemployed in many devices.

The resulting titanium nitride is spongy, with a rough surface, and hasa lower density and a higher resistivity than conventionally formedtitanium nitride. FIG. 3 shows than about 300 microOhm-cms, preferablygreater than 500 microOhm-cms, more preferably greater than 1000microOhm-cms.

A layer or film of titanium nitride having the lower density and higherresistivity noted for any portion of the layer or film with a thicknessgreater than about 20 angstroms will have the advantageous propertiesdescribed herein.

When low-density, high-resistivity titanium nitride is used adjacent tothe antifuse, the pre-rupture leakage current across the antifuse isvery much less than when conventionally-formed titanium nitride is used,as shown in FIG. 4. The plot of FIG. 4 is probability plot, in whicheach data point is the measurement of one device on a wafer. Theprobability plot allows the distribution for many devices to be shown,giving statistical significance to the data.

The layer of low-density, high-resistivity titanium nitride in thisexample is adjacent to an antifuse, which is intended, before rupture,to allow minimal leakage current. The antifuse has a roughly circularshape with a diameter of about 0.15 μm. The cross-sectional area forwhich the leakage is measured, then, is:π×((0.15 μm)/2)²=0.0177 μm²

In this case the median leakage current, with 2 volts applied across theantifuse, was reduced from 5.5×10⁻¹⁰ amps for conventional densetitanium nitride, shown on curve B, to a median of close to 3×10⁻¹² ampsfor low-density, high-resistivity titanium nitride, shown on curve A; animprovement of greater than three orders of magnitude. Actual values forleakage current will vary with the thickness and material of thedielectric used, the dimensions of the device, etc., but it can beassumed that use of the low-density, high-resistivity titanium nitride(or one of the other materials named) used in the present invention willdecrease leakage current to less than one-tenth the leakage current inthe same device when conventionally formed titanium nitride (or itscounterpart) is used. A material of the same chemical composition but adifferent density, resistivity, and/or stoichiometry is referred to as“an analogous material”; for shown on curve B, to a median of close to3×10⁻¹² amps for low-density, high-resistivity titanium nitride, shownon curve A; an improvement of greater than three orders of magnitude.Actual values for leakage current will vary with the thickness andmaterial of the dielectric used, the dimensions of the device, etc., butit can be assumed that use of the low-density, high-resistivity titaniumnitride (or one of the other materials named) used in the presentinvention will decrease leakage current to less than one-tenth theleakage current in the same device when conventionally formed titaniumnitride (or its counterpart) is used. A material of the same chemicalcomposition but a different density, resistivity, and/or stoichiometryis referred to as “an analogous material”; for example, stoichiometric,high-density titanium nitride is an analogous material to low-density,high-resistivity titanium nitride.

It has been shown that leakage current of less than 10⁻¹¹ amps can beachieved across a pre-ruptured antifuse with an area of about 0.0177μm². Thus, normalizing for the area of the antifuse, a memory arraycomprising memory cells on a die, wherein the memory cells comprisediode portions and an antifuse, and wherein the median leakage currentacross the antifuse for the memory cells on the die is less than about1.77×10⁻¹³ amps/μm², can be formed. The advantages of the low-density,high-resistivity titanium nitride and analogous materials would benefitmemory arrays including diode portions formed of monocrystalline siliconas well as polysilicon.

The forward current after rupture is also significantly better than whenstandard titanium nitride is used, as shown in FIG. 5. Low-density,high-resistivity titanium nitride is used on curve A, and conventional,denser titanium nitride on curve B.

Method of Making

A detailed description of a method for making the low-density,high-resistivity titanium nitride used in the present invention isprovided for illustration. It will be understood, however, that some ofthese detailed steps can be altered, supplemented, or omitted whilestill falling within the scope of the invention.

In embodiments of the monolithic three dimensional memory arraydescribed in the '470 application, semiconductor elements comprisingdiodes are formed by depositing doped polycrystalline silicon, hereincalled polysilicon, which is then patterned and etched into posts. Thegaps between the semiconductor elements are filled with dielectric, thenthe dielectric planarized, for example by chemical mechanical polishing(CMP) or etchback, to expose the tops of the semiconductor elements. Inpreferred embodiments, a silicon dioxide antifuse is then thermallygrown on the polysilicon semiconductor elements.

The next layer to be deposited is the low-density, high-resistivitytitanium nitride. The wafer is placed in an Applied Materials Endura IMPchamber. After an initial flow of 25 standard cubic centimeters perminute (sccm) of Ar and 45 sccm of N₂, a plasma is generated by applyingRF power inside the chamber, and DC power of 4000 watts is applied.During deposition N₂ flow is reduced to 28 sccm. No self-bias is appliedto accelerate metal ions toward the wafer surface. Deposition continuesfor 41 seconds, yielding about 200 angstroms of titanium nitride. Duringdeposition, pressure in the chamber should be measured at between about15 and about 40 mTorr, preferably between about 20 mTorr and about 40mTorr, preferably about 20 mTorr. After deposition is complete, thewafer is moved to another chamber for deposition of the next layer,preferably tungsten deposited by chemical vapor deposition (CVD.)

Low-density, high-resistivity titanium nitride can also be produced in astandard PVD chamber, one designed with no capacity for self-biasdirecting ions normal to the deposition substrate. For example, theApplied Materials Endura PVD chamber can be used. During standardoperation, titanium nitride is deposited in this and similar chambers at0.5-5 mTorr. To deposit low-density, high-resistivity titanium nitride,the pressure in the PVD chamber during sputter must be increased toabout 20 mTorr. It is believed the higher pressure decreases the energyof the sputtered atoms before they reach the surface of the wafer.

Pressure in a PVD chamber can be controlled by (among other things) thegate valve. Typically the gate valve has three settings: full (fullyopen), mid (partially open), and closed. Nearly all PVD recipes use thegate valve in the full position. To reach 20 mTorr, the chamber must runwith the valve in the mid position, which slows escape of gases in thechamber, increasing the pressure. The mid position is adjusted duringtool startup to achieve this pressure, and is typically not adjustedagain for the life of the chamber.

The mid position of the valve should be adjusted to select the desiredpressure. This can be done according to manufacturers' instructions.

Alternatively, the antifuse layer 104 (of FIG. 1) can be formed ofsilicon nitride instead of silicon dioxide. This is preferably done byforming the PN diode 102 according to the teachings of the '470application, and filling and planarizing to expose the top of PN diode102. Next, silicon nitride is thermally grown, for example in a rapidthermal annealing tool at 750 to 800 degrees Celsius, flowing 4liters/minute of NH₃ for 60 seconds at atmospheric pressure, with atemperature ramp rate of 50 degrees C. per second, forming a layer ofsilicon nitride preferably about 23 angstroms thick. The silicon nitrideantifuse could be deposited instead. This layer of silicon nitrideserves as antifuse 104. The low-density, high-resistivity titaniumnitride layer is formed next, as before.

The leakage current associated with a silicon nitride antifuse isgenerally higher than, for example, a silicon dioxide antifuse. Pairinga silicon nitride with a higher-resistivity conductor reduces leakagecurrent across the silicon nitride antifuse significantly. Siliconnitride antifuses have the advantage of a faster time to rupture thansilicon dioxide antifuses, allowing memory cells to be programmedfaster.

Antifuses formed of silicon nitride can also be ruptured at a lowerbreakdown field, thus requiring less power. In the device described inthe '470 application, for example, in top antifuse embodiments when thediameter of the diode is about 0.15 μm, a voltage of about 10 volts isrequired to reliably rupture antifuses formed of silicon dioxide. Whensilicon nitride antifuses are used in the same device at the same diodediameter, the antifuse can be ruptured at lower voltages, for example6-8 volts. This allows memory cells to be scaled to smaller devices, aslower voltages allow smaller programming transistors to be used.

To form analogous low-leakage barriers using tungsten nitride, tantalumnitride, titanium tungsten, tungsten, or aluminum, similar fabricationmethods can be used. A tungsten or tantalum target can be sputtered withN₂ in an IMP chamber with no self-bias, or in a PVD chamber withincreased pressure to make tungsten nitride or tantalum nitride; or atitanium tungsten target can be sputtered under the conditions describedto make titanium tungsten. A tungsten or aluminum target can besputtered with a neutral gas, like Ar. PVD sputtering in high-pressureconditions should create the low-density, high-resistivity compoundsused in the present invention.

The resulting low-density, high-resistivity counterpart of each of thesesputtered metals or compounds will have a density at most 75 percent ofthe metal or compound's theoretical density. For example, thetheoretical density of aluminum is 2.7 grams/cm³; thus its low-density,high-resistivity counterpart has a density of 2.03 grams/cm³ or less.Similarly, the theoretical density of tungsten is 19.3 grams /cm³; thusits low-density, high-resistivity counterpart has a density of about14.48 grams/cm³ or less. Tantalum nitride has a theoretical density ofabout 16.3 grams/cm³; thus its low-density, high-resistivity counterparthas a density of about 12.23 grams/cm³ or less.

The methods used to form the low-density, high-resistivity titaniumnitride layer used adjacent to the antifuse in the monolithicthree-dimensional memory array of the '470 application, or the othermetals named, can, of course, be used to create a similar layer in otherdevices that require a low-leakage barrier.

Methods to deposit the low-density, high-resistivity titanium nitride(and the other named metals) used in the present invention in an IMPchamber and a standard PVD chamber have been disclosed, but clearlyother methods could be envisioned. Any method which produceslow-density, high-resistivity titanium nitride, or the other namedmetals, as described herein will fall within the scope of the invention.

Use in Devices

The following section will describe the use of low-densityhigh-resistivity titanium nitride, tungsten nitride, tantalum nitride,titanium tungsten, tungsten, or aluminum in devices using a low-leakagebarrier. For simplicity, the examples given herein will name titaniumnitride as the metal used, but it will be apparent to one skilled in theart that the other named metals, tungsten nitride, tantalum nitride,titanium tungsten, tungsten or aluminum could be used instead in any ofthese devices or in other devices. Clearly tungsten is a lessadvantageous choice if the layer is directly on and in contact with anunderlying oxide, since, as noted earlier, tungsten doesn't adhere tosilicon dioxide; and aluminum is less advantageous when formed adjacentto an oxide, as it tends to reduce oxides. It is routine for the skilledpractitioner to choose compatible materials.

Many devices which require low leakage current across a dielectric canbenefit from use of this low-density, high resistivity titanium nitride.Several non-limiting examples are provided. In each device, suggestedsteps and materials are provided for making the device. It will beunderstood that these steps and materials are provided for clarity, butthat steps could be changed, added, or omitted while the device and/ormethods to produce it still fall within the scope of the invention.

Schottky Diode with Junction Antifuse

A Schottky diode is a rectifying contact between a semiconductor and ametal. An incipient Schottky diode can be formed in many configurations.This example will describe a Schottky diode formed at the intersectionof two rails, the semiconductor in one rail, the metal in the other, thetwo separated by an antifuse, as taught in Vyvoda, U.S. patentapplication Ser. No. 10/440882, “Rail Schottky Device and Method ofMaking,” filed May 19, 2003, assigned to the assignee of the presentinvention and hereby incorporated by reference. This device is anincipient Schottky diode, which becomes a Schottky diode when theantifuse is ruptured. Some of the methods and details described here byway of illustration are described more fully in Vyvoda. For simplicity,not all of the details of Vyvoda are reproduced in this description, butnone of the teaching of Vyvoda is intended to be excluded.

Turning to FIG. 6, a plurality of incipient Schottky diodes using thelow-density, high-resistivity titanium nitride used in the presentinvention can be formed by depositing a doped semiconductor layer 12,for example doped polysilicon, preferably by in situ doping, thenpatterning and etching semiconductor layer 12 into substantiallyparallel rails. A rail can include other layers below semiconductor rail12, and can be formed over a semiconductor substrate (not shown.) Next adielectric (not shown) is deposited over and between semiconductor rails12, then planarized, for example by CMP or etchback, to expose the topsof the rails. An antifuse layer 14 is formed on top of layer 12.Antifuse layer 12 is a dielectric antifuse capable of being ruptured.Antifuse layer 14 can also be deposited. If semiconductor layer 12 isformed of doped polysilicon, antifuse layer 14 can be thermally grownsilicon dioxide. In this case it will exist only over semiconductorrails 12 but not between them, as it derives its silicon from thepolysilicon of semiconductor layer 12; if it is deposited it will existbetween the rails as well.

Next a low-density, high-resistivity titanium nitride layer 16 ispreferably formed according to the methods disclosed herein, for exampleby deposition in an IMP chamber with no self-bias, or by deposition in astandard PVD chamber with no self-bias and with pressure increased to,for example, 20 mTorr. A thickness of, for example, about 200 angstromsof titanium nitride can be formed. The titanium nitride of Vyvoda iscreated by PVD without self-bias, with no teaching to increase thepressure in the chamber, and thus is normal high-density titaniumnitride, not the low-density, high-resistivity titanium nitridedescribed herein.

In preferred embodiments disclosed in Vyvoda, the next layer 18 is dopedpolysilicon. Layer 18 could also be a metal, for example tungsten.Tungsten can be deposited, for example by CVD. Next tungsten orpolysilicon layer 18 and titanium nitride layer 16 are patterned andetched to form rails substantially perpendicular to underlyingsemiconductor rails 12. Semiconductor layer 12, antifuse layer 14, andtitanium nitride layer 16 form an incipient Schottky diode. Afterantifuse 14 is ruptured by applying high current, semiconductor layer 12and titanium nitride layer 16 form a Schottky diode.

As in the PN diode example of the '470 application, it would be expectedthat the forward current after rupture of the antifuse would be improvedby use of the low-density high-resistivity titanium nitride described.

Also as in the PN diode described above, antifuse 14 can advantageouslybe formed of silicon nitride for a memory cell with faster programmingtime.

Field Effect Transistor

A field effect transistor can make use of the low-leakage layer used inthe present invention. Turning to FIG. 7, such a field effect transistoris formed on channel region 20, which may be polysilicon,monocrystalline silicon, silicon on insulator, or some othersemiconductor material. A dielectric layer 22 is grown or deposited onchannel region 20, then layer 24 of low-density, high-resistivitytitanium nitride is formed on dielectric layer 22. The entire gate canbe of titanium nitride, or a layer 26 of some other conductive material,for example tungsten, can be formed on top. Alternately, layer 24 can below-density, high-resistivity titanium nitride, while layer 26 is morestandard higher-density, lower-resistivity titanium nitride formedconventionally. Gate layers 26 and 24 and dielectric layer 22 are thenpatterned and etched to form a gate and gate dielectric. Source S anddrain D are formed, for example, by ion implantation.

SONOS-Type Memory Cell

A SONOS-type memory cell, shown in FIG. 8, comprises a channel 30 (withadjacent source S and drain D), a tunnel dielectric 32, a chargetrapping layer 34, a blocking dielectric 36, and a gate electrode, herecomprising conductive layers 38 and 40. Typically in a SONOS device, thechannel is formed of silicon, the tunnel dielectric of oxide, the chargetrapping layer of nitride, the blocking dielectric of oxide, and thegate electrode of silicon; the silicon-oxide-nitride-oxide-silicon stackgives the SONOS device its name, though alternate materials may be usedfor each layer named. The term “SONOS-type” device or memory cell meansa charge trapping device with a tunnel dielectric, a dielectric chargetrapping layer and a blocking dielectric, all between a channel and agate electrode, irrespective of materials.

When a voltage is applied to the gate electrode 38/40, charge carrierstunnel through the tunnel dielectric 32 and are trapped in the chargetrapping layer 34. The presence or absence of stored charge in chargetrapping layer 34 can be sensed, and distinguishes a programmed cellfrom an unprogrammed cell.

A method is provided to form a SONOS-type memory cell using thelow-density, high-resistivity titanium nitride used in the presentinvention, though many other methods to form a SONOS device are knownand can be used with the titanium nitride used in the present invention.

The SONOS-type memory cell will be formed on channel region 30, whichmay be polysilicon, monocrystalline silicon, silicon on insulator, orsome other semiconductor material. A dielectric layer 32 is grown ordeposited on channel region 30; for example a thin layer of silicondioxide can be thermally grown on a silicon or polysilicon substrate. Acharge trapping layer 34, for example silicon nitride, is formed ontunneling dielectric 32. A blocking dielectric 36, for example depositedsilicon dioxide, is formed on charge trapping layer 34.

On and in contact with blocking dielectric 36, low-densityhigh-resistivity titanium nitride layer 38 is formed, preferably by theunbiased high-pressure PVD methods mentioned earlier. The gate electrodelayer stack optionally also includes layer 40, preferably of tungsten,though standard titanium nitride or other conductors or semiconductorscan be used instead. Layers 40, 38, 36, 34, and 32 are patterned andetched to form the SONOS-type memory cell. Source S and drain D regionsare formed by ion implantation.

Floating Gate Memory Cell

A floating gate memory cell, shown in FIG. 9, comprises a channel 50(with adjacent source S and drain D), a tunnel dielectric 52, a floatinggate 54, a blocking dielectric 56, and a control gate, here comprisingconductive layers 58 and 60.

When a voltage is applied to the control gate 58/60, charge carriers areinjected and trapped in floating gate 54, which is typically formed of asemiconductor. The presence or absence of stored charge in floating gate54 can be sensed, and distinguishes a programmed cell from anunprogrammed cell.

A method is provided to form a floating gate memory cell using thelow-density, high-resistivity titanium nitride used in the presentinvention, though many other methods to form a floating gate memory cellare known and can be used with the low-density high-resistivity titaniumnitride used in the present invention.

The floating gate memory cell will be formed on channel region 50, whichmay be polysilicon, monocrystalline silicon, silicon on insulator, orsome other semiconductor material. A dielectric layer 52 is grown ordeposited on channel region 50; for example a thin layer of silicondioxide can be thermally grown on a silicon or polysilicon substrate. Afloating gate layer 54, for example of doped polysilicon, is formed ontunneling dielectric 52. A blocking dielectric 56, for example depositedsilicon dioxide, is deposited on floating gate layer 54.

On and in contact with blocking dielectric 56, low-densityhigh-resistivity titanium nitride layer 58 is formed, preferably by theunbiased, high-pressure PVD methods mentioned earlier. The control gatelayer stack optionally also includes layer 60, preferably of tungsten,though standard titanium nitride or other conductors or semiconductorscan be used instead. Layers 60, 58, 56, 54, and 52 are patterned andetched to form the floating gate memory cell. Source S and drain Dregions are formed by ion implantation.

Capacitor

A capacitor stores charge by using a dielectric to separatecharge-bearing layers of conductor or semiconductor material. FIG. 10shows a very simple capacitor.

Substrate 70 is a conductor or a semiconductor, preferably dopedmonocrystalline or polycrystalline silicon between field oxide regions72. A layer of low-density, high-resistivity titanium nitride 74 isformed on substrate 70. A dielectric 76 is formed next, then a secondlayer 78 of low-density, high-resistivity titanium nitride is formedatop the dielectric 76. Titanium nitride layer 78, dielectric layer 76,and titanium nitride layer 74 are patterned and etched to form acapacitor.

In this example, low-density, high-resistivity titanium nitride wasformed below and in contact with dielectric 76, as well as above and incontact with dielectric 76. Clearly either one or the other oflow-density, high resistivity titanium nitride layers 74 or 78 could beomitted and replaced with some other conductor or semiconductor.

Monolithic three dimensional memories are described in Johnson et al.,U.S. Pat. No. 6,034,882, “Vertically Stacked Field ProgrammableNonvolatile Memory and Method of Fabrication”; in Johnson, U.S. Pat. No.6,525,953, “Vertically Stacked Field Programmable Nonvolatile Memory andMethod of Fabrication”; Knall et al., U.S. Pat. No. 6,420,215, “ThreeDimensional Memory Array and Method of Fabrication”; Lee et al., U.S.patent application Ser. No. 09/927648, “Dense Arrays and Charge StorageDevices, and Methods for Making Same,” filed Aug. 13, 2001; Walker etal., U.S. application Ser. No. 10/335089, “Method for FabricatingProgrammable Memory Array Structures Incorporating Series-ConnectedTransistor Strings,” filed Dec. 31, 2002; Scheuerlein et al., U.S.application Ser. No. 10/335078, “Programmable Memory array StructureIncorporating Series-Connected Transistor Strings and Methods forFabrication and Operation of Same,” filed Dec. 31, 2002; and Vyvoda etal., all assigned to the assignee of the present invention and hereinincorporated by reference. The memory cells in these memory arrays arediodes, incipient diodes, or charge-storage cells such as SONOS-type orfloating gate cells. Low-density, high-resistivity titanium nitride,tungsten nitride, tantalum nitride, titanium tungsten, tungsten, oraluminum according to the present invention can be used in any of thesememory arrays when a low-leakage dielectric separating conductors orsemiconductors is described. The low-density, high-resistivity materialused in the present invention can be formed adjacent the dielectric tomake a very low-leakage layer. The low-density, high-resistivitymaterial can be used on any level of memory.

In some monolithic three-dimensional memory arrays taught in theseincorporated patents and applications, the memory cells comprise diodeportions and antifuses. The diode portions may be found in either railsor pillars. A silicon nitride antifuse can be advantageously paired withthe low-density high-resistivity material (titanium nitride, tungstennitride, tantalum nitride, titanium tungsten, tungsten, or aluminum)described herein.

The foregoing detailed description has described only a few of the manyforms that this invention can take. For this reason, this detaileddescription is intended by way of illustration, and not by way oflimitation. It is only the following claims, including all equivalents,which are intended to define the scope of this invention.

1. A method for forming titanium nitride in a semiconductor devicecomprising: providing a surface for a semiconductor device; anddepositing a film of titanium nitride on the surface by physical vapordeposition wherein, for any portion of the film more than about 20angstroms thick, the density of the titanium nitride is less than about4.0 grams per cubic cm.
 2. The method of claim 1 wherein, for anyportion of the film more than about 20 angstroms thick, the resistivityof the titanium nitride is greater than about 300 microOhm-cms.
 3. Themethod of claim 1 wherein, for any portion of the titanium nitride filmmore than about 20 angstroms thick, the resistivity of the titaniumnitride is greater than about 1000 microOhm-cms.
 4. The method of claim1 wherein, for any portion of the titanium nitride film more than about20 angstroms thick, the density of the titanium nitride is less thanabout 4.0 grams per cubic cm.
 5. The method of claim 4 wherein, for anyportion of the titanium nitride film more than about 20 angstroms thick,the pressure during physical vapor deposition is greater than about 15mTorr.
 6. The method of claim 5 wherein, for any portion of the titaniumnitride film more than about 20 angstroms thick, the pressure duringphysical vapor deposition is greater than about 18 mTorr.
 7. The methodof claim 6 wherein, for any portion of the titanium nitride film morethan about 20 angstroms thick, the pressure during physical vapordeposition is greater than or equal to about 20 mTorr.
 8. The method ofclaim 1 wherein the titanium nitride film is in contact with adielectric.
 9. The method of claim 8 wherein the dielectric is disposedbetween the titanium nitride film and a conductive or semiconductivelayer.
 10. A method for making a thin film transistor comprising:forming a polysilicon layer; forming a silicon dioxide layer in contactwith the polysilicon layer; forming a titanium nitride layer in contactwith the silicon dioxide layer wherein, for any portion of the titaniumnitride layer more than about 20 angstroms thick, the resistivity of thetitanium nitride is greater than about 300 microOhm-cms and the densityof the titanium nitride is less than about 4.25 grams per cubic cm; andpatterning and etching the titanium nitride.
 11. The method of claim 10wherein the step of forming the silicon dioxide layer comprisesthermally growing silicon dioxide.
 12. The method of claim 10, wherein,for any portion of the titanium nitride layer more than about 20angstroms thick, the step of forming the titanium nitride layercomprises physical vapor deposition of titanium nitride withsubstantially no self-bias and pressure greater than about 15 mTorr. 13.The method of claim 10, wherein, for any portion of the titanium nitridelayer more than about 20 angstroms thick, density of the titaniumnitride is less than about 4.0 grams per cubic cm.
 14. A method forforming titanium nitride in a semiconductor device comprising: providinga surface for a semiconductor device; and depositing on the surface afilm of titanium nitride by physical vapor deposition wherein, for anyportion of the film more than about 20 angstroms thick, the depositionis performed with substantially no self-bias and with pressure greaterthan about 15 mTorr.
 15. The method of claim 14, wherein the titaniumnitride is in contact with a dielectric layer.
 16. The method of claim15, wherein the dielectric layer is silicon dioxide.
 17. The method ofclaim 15, wherein the dielectric layer is silicon nitride.
 18. A methodfor forming titanium nitride for use in a semiconductor devicecomprising: providing a surface for a semiconductor device; on thesurface, depositing titanium nitride wherein, for any portion of thetitanium nitride layer more than about 20 angstroms thick, theresistivity of the titanium nitride is greater than about 300microOhm-cms and the ratio of nitrogen to titanium is greater than about1.2:1.
 19. The method of claim 18 wherein, for any portion of thetitanium nitride layer more than about 20 angstroms thick, theresistivity of the titanium nitride is greater than about 1000microOhm-cms.